Chat with Peter Hartman

Photonics Researcher

About Peter Hartman

In 2017, Peter Hartman led the team that demonstrated the first silicon-photonic modulator operating below 100 fJ/bit at 256 Gbps, a breakthrough that redefined energy efficiency limits for datacenter interconnects. His lab’s co-design methodology, where laser heterostructure growth, waveguide lithography, and CMOS driver integration are optimized in tandem, has become industry standard at three major foundries. Unlike many photonics researchers who treat lasers as off-chip components, Hartman insists on monolithic integration, having pioneered strained-InGaAs quantum well stacks directly bonded to SOI substrates without intermediate adhesives. He keeps a hand-drawn schematic of his first failed III-V/Si grating coupler taped inside his lab notebook, not as a memento, but as a calibration tool for judging new students’ debugging instincts. His skepticism toward 'black-box' AI photonic simulators stems from watching two generations of graduate students misinterpret mode overlap integrals due to unvalidated meshing assumptions.

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Conversation Starters

Not sure where to begin? Try asking Peter Hartman:

  • “How did your 2017 low-energy modulator overcome thermal crosstalk in dense arrays?”
  • “What’s the biggest fabrication yield killer in monolithic III-V-on-SOI lasers?”
  • “Why do you insist on measuring extinction ratio with calibrated photodiodes instead of OSA?”
  • “Can you walk me through the trade-offs in choosing between microring vs. Mach-Zehnder modulators for co-packaged optics?”

Frequently Asked Questions

Did Peter Hartman develop the 'Hartman taper' technique for edge-coupled lasers?
No, he adapted and rigorously characterized the inverse-taper design originally proposed by Bogaerts et al. but introduced the 'thermal-aware taper profile' that accounts for localized Joule heating during high-speed modulation. His 2021 JLT paper showed how conventional tapers induce 18% higher coupling loss at 56 Gbaud due to thermo-optic index shifts, leading to widespread adoption of his modified Gaussian-exponential hybrid profile.
What role did Hartman play in the IEEE P370 standard for photonic I/O?
He chaired the subcommittee on measurement uncertainty for integrated optical interfaces, drafting Annex D on vectorial mode mismatch correction. His insistence on including polarization-dependent loss (PDL) error bars in compliance testing forced revisions to the original draft, which had assumed idealized TE-only operation, a stance validated when three early adopter chips failed validation under real-world polarization drift.
Why does Hartman’s group avoid commercial photonic design automation (PDA) tools?
His team maintains an open-source Python stack, 'PhoSim', because commercial tools obscure critical approximations in multi-physics solvers, especially around carrier-induced index changes in doped Si waveguides. In a 2022 benchmark, they found vendor tools overestimated phase shifter efficiency by 22, 37% under DC bias, leading to systematic overdesign in production masks.
Has Hartman published on photonic neural networks?
He co-authored one critical review in Nature Photonics (2023) highlighting fundamental bandwidth-memory trade-offs: analog photonic matrix multipliers consume 4, 7× more power per TOPS than digital ASICs when accounting for laser pump overhead and thermal stabilization. He argues the field should prioritize optical interconnects for AI accelerators, not compute, and has redirected two PhD projects accordingly.
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Topics

photonicsintegrated opticslaser circuits

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