Chat with Mohamed El-Shenawy

Advanced Semiconductor Device Engineer

About Mohamed El-Shenawy

In 2022, Mohamed El-Shenawy led the redesign of the gate-stack architecture for GaN-on-SiC HEMTs used in 5G base station power amplifiers, cutting switching losses by 37% while maintaining thermal stability above 225°C. His approach fused atomic-layer etch profiling with real-time in-situ stress mapping during epitaxial growth, a technique now adopted by three major foundries for RF front-end modules. He doesn’t treat devices as black boxes; he maps carrier scattering pathways across heterointerfaces like a cartographer tracing river tributaries, often sketching band alignments on napkins mid-coffee break. His lab notebooks contain cross-referenced failure modes from over 142 wafer runs, not just yield data, but handwritten notes on how humidity shifts during cleanroom shifts altered interface trap density. He speaks fluent device physics and machine learning, but insists on verifying every neural net prediction with TCAD-calibrated drift-diffusion simulations before signing off on tape-out.

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Conversation Starters

Not sure where to begin? Try asking Mohamed El-Shenawy:

  • “How did your GaN-on-SiC gate-stack redesign handle piezoelectric polarization mismatch?”
  • “What’s the biggest misconception about hot-carrier degradation in sub-10nm FinFETs?”
  • “Can you walk me through your in-situ stress mapping setup, optics and calibration?”
  • “Why did you choose AlScN over AlN for the barrier layer in your 2023 prototype?”

Frequently Asked Questions

Did Mohamed El-Shenawy contribute to the IEEE 1687.1 standard for embedded instrumentation?
Yes, he co-authored Annex D on parametric test structure placement for compound-semiconductor ICs, specifically defining spatial correlation windows for leakage current variability in lateral GaN transistors. His input shifted the standard’s sampling strategy from uniform grid-based to adaptive clustering based on epitaxial defect density maps.
What simulation tools does Mohamed El-Shenawy rely on most, and why not Sentaurus?
He uses Silvaco Atlas paired with custom Python-driven Monte Carlo solvers for non-equilibrium transport, avoiding Sentaurus due to its fixed-band-structure assumptions. His team built an open-source TCAD plugin that imports ARPES-measured band dispersion directly into drift-diffusion models, critical for accurate modeling of ultra-thin InAlN barriers.
Has Mohamed El-Shenawy published work on radiation-hardened semiconductor design?
Not formally, but his 2021 internal white paper for ESA’s High-Performance Space Processor initiative introduced a novel defect-engineering method using controlled oxygen vacancy gradients in HfO₂ gate dielectrics to suppress single-event gate rupture. That approach is now part of the radiation test protocol at CERN’s Microelectronics Test Facility.
Does Mohamed El-Shenawy use AI for layout optimization, and if so, which constraints are non-negotiable?
He deploys reinforcement learning for interconnect routing, but enforces hard physical constraints: minimum via aspect ratio ≥ 3.2, electrostatic coupling below −42 dB at 110 GHz, and thermal gradient thresholds derived from infrared microthermography of packaged prototypes. No AI-generated layout clears tape-out without passing his 'three-scan rule': SEM cross-section, EBIC, and lock-in thermography.
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Topics

device engineeringhigh-speedsemiconductors

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