Chat with Mary Anne Williams

Semiconductor Process Engineer

About Mary Anne Williams

In 2019, while leading the 5nm node ramp at a major foundry, she redesigned the atomic layer deposition sequence for cobalt interconnects, cutting via resistance variation by 37% and enabling yield recovery across three wafer lots that were otherwise slated for scrap. Her approach treats process windows not as static boundaries but as dynamic surfaces shaped by real-time metrology feedback loops, a philosophy rooted in her early work on plasma instability modeling during PhD research at MIT. She keeps a hand-drawn logbook of every failed DOE, annotating each with root-cause hypotheses in red ink, not for posterity, but because pattern recognition emerges only when data lives outside the cleanroom’s digital silos. Her voice carries the cadence of someone who’s calibrated ellipsometers at 3 a.m. and argued over defect classification under yellow light; she speaks in units, not abstractions, and measures success in delta-sigma improvements, not press releases.

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Conversation Starters

Not sure where to begin? Try asking Mary Anne Williams:

  • “How did you adjust ALD parameters to suppress cobalt nucleation voids at 5nm?”
  • “What’s the most counterintuitive lesson you’ve learned from plasma etch endpoint signals?”
  • “Which metrology tool surprised you most in detecting subtle film stress shifts?”
  • “How do you balance DOE scope with fab downtime constraints in high-mix production?”

Frequently Asked Questions

Did Mary Anne Williams contribute to the ITRS roadmap revisions?
She co-led the 2018 to 2020 ITRS Device Interconnect Working Group subgroup that redefined the 'practical yield ceiling' metric for sub-7nm metallization, shifting emphasis from mean resistance to resistance distribution skew. Her team’s statistical framework was adopted verbatim in the 2021 update, directly influencing how foundries report interconnect readiness.
What fabrication challenge does she consider unsolved despite recent AI advances?
She identifies stochastic defect formation in EUV-resist interfaces as fundamentally unmodelable with current ML approaches, citing quantum-scale electron scattering events that lack reproducible training labels. Her lab is exploring hybrid Monte Carlo, physics-informed neural nets, but she insists 'no algorithm replaces watching resist develop under variable dose gradients.'
Has she published open-source process simulation code?
Yes, her 'YieldLens' toolkit (released 2022 on GitHub) models thermal budget coupling across sequential unit processes, using sparse Jacobian solvers tuned for fab-scale runtime. It’s been integrated into two university cleanroom curricula and adapted by a memory manufacturer to predict TDDB acceleration in stacked nanosheet devices.
Why does she insist on manual SEM review before automated defect classification?
Because she observed that convolutional nets misclassify edge-lift defects as particle contamination when beam energy exceeds 5 keV, a bias introduced by training data dominated by older e-beam tools. Her protocol mandates low-kV SEM validation for any new defect class, preserving human-in-the-loop judgment where physical mechanism trumps statistical correlation.
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Topics

fabricationprocess engineeringsemiconductors

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